Bay BayStack 400-ST1 Instrukcja Użytkownika Pobierz pdf (Strona 1)

(12)

United

States

Patent

Poulter

al.

US007233601B1

7,233,601

Jun.

19,

2007

(10)

Patent

N0.:

(45)

Date

Patent:

(54)

CASCADE

ARCHITECTURE

AND

6,330,245

12/2001

Brewer

a1.

............

370/424

OPERATION

FOR

PACKET-BASED

6,373,840

4/2002

Chen

...........

370/360

COMMUNICATION

SYSTEMS

6,393,026

B1*

5/2002

Irwin

.............

370/401

6,428,338

8/2002

Yasufuku

al.

.........

439/310

(75)

Inventors:

Alan

Poulter,

Bedford

(GB);

Quang

Tran,

Hemel

Hempstead

(GB);

(

Ommue

)

Sharon

Wiles,

Bovingdon

(GB);

FOREIGN

PATENT

DOCUMENTS

David

LaW,

Kempston

(GB);

Paul J

Moran,

Hemel

Hempstead

(GB);

0158364

10/1985

Christopher

Walker,

Watford

(GB)

1nue

(73)

Assignee:

Corporation,

Marlborough,

OTHER

PUBLICATIONS

Bay

Networks,

Installing

the

BayStack

400-ST1

Cascade Module,

(

)

Notice:

Subject

any

disclaimer,

the

term

this

PP~

1-38,

NOV

1993*

_ _

patent

extended

or adjusted

under

3COM,

SuperStack

Switch

4400

Cascade

Module

User

Guide,

pp.

U.S.C.

154(1))

956

days.

1'7’

Ma“

200”

Primary

ExamineriFrank

Duong

(21)

Appl.

N0.:

09/662,158

(57)

ABSTRACT

(22)

F1led:

Sep.

14,

2000

(30)

Foreign

Application

Priority

Data

connectmg

umt

for

use

a~system

compr1s1ng

a stack

network

commun1cat1on

un1ts

hav1ng

cascade

connec

Aug.

2000

(GB)

...............................

00187138

tion

has

three

ports

having

lines

for

forwarding

and

receiv

ing

data

packets

and

for

forwarding

and

receiving

control

(51)

Int-

Cl-

messages.

The

connecting

unit

increments

?rst

signal

H04L

12/40

(2006-01)

value

de?ning

identi?cation

number

received

Way

(52)

US.

Cl.

....................................................

370/439

control

message

?rst

port,

provides

the

received

signal

(58)

Field

Classi?cation

..............

370/217,

value

Way

control

message

the

third

port

and

370/218,

221,

222,

224, 249, 403, 404, 405,

provides

the

incremented

signal

value

Way

control

370/406,

452, 460,

907

message

the

second

port.

The

connecting

unit

also

See

application

?le

for

complete

history.

receives

second

signal

value

de?ning

active

unit

count

Way

control

message

the

?rst

port

and

provides

the

(56)

References

Clted second

signal

value,

incremented

not

dependence

PATENT

DOCUMENTS

control

message

received

the

third

port,

control

message

the

second

port.

The

?rst

signal

values

(UnitlDs)

4,561,088

12/1985

Champlln

a1~

are

used

establish

the

numbering

the

units

the stack

gupta

ettall'

""""""

and

the

second

signal

values

are

used

compute

count

, ,

earcee

‘

~ -

6,038,618

3/2000

Beer

al.

710/18 the

acme

umts

“1

the

Stack‘

6,314,110

11/2001

Chin

al.

................

370/468

6,327,242

12/2001

Amicangioli

a1.

.....

370/216

31 Claims, 19

Drawing

Sheets

T‘\,

CST-Flo]

Colnlrol

Bushy“,

“-

‘—o

Z3_

_ r\/

‘K

57%

r\_/

CNS

message

TX/RX,

LinkStatus,

_—E

UnitlD

and

AUCount

‘g’

algorithms

V V V

13:10:12“

Collard

C3559‘

BusVcc

1 2 3 4 5 6 ... 32 33

Podsumowanie treści

Strona 1 - Patent:

(12) United States Patent Poulter et al. US007233601B1 US 7,233,601 B1 Jun. 19, 2007 (10) Patent N0.: (45) Date of Patent: (54) CASCADE ARCHITECTURE A

Strona 2 - 7,233,601

U.S. Patent Jun. 19, 2007 Sheet 8 0f 19 US 7,233,601 B1 Conlrol Comrol OUT IN A TX Rx BusVcc A P011 '0 O :1 9 Modular 57 7 _ f\_/ 53 \ / v N 56

Strona 3 - “DEBUG-[1L

U.S. Patent Jun. 19, 2007 Sheet 9 0f 19 US 7,233,601 B1 91 90 \ A J Y Y Pfeamble Data- 4 Bytes (32 Bits) 7 l 6 I 5 ' 4 3 2 1 0 I _I l Byte O Unit

Strona 4

U.S. Patent Jun. 19, 2007 Sheet 10 0f 19 US 7,233,601 B1 7 Q 6 I 5 I 4 3 2 1 0 l # I ByteO L UnitlDl31O] tpPolUp tpPolDn Active T-Piece I l 7 s 5 4

Strona 5

U.S. Patent Jun. 19, 2007 Sheet 11 0f 19 US 7,233,601 B1 FIG.14 60 Q / LinkStatus Logic Control OU it? 11 66 3 Control I

Strona 6

U.S. Patent Jun. 19, 2007 Sheet 12 0f 19 US 7,233,601 B1 High during Idle, Unit 2 Low during Idle, Unit 2 ID Logic FPGA Low during Idle. Unit I High d

Strona 7 - 61(\/.®M_=mw

U.S. Patent Modular Porl Dam RX Dam TX Control IN signals shown Jun. 19, 2007 Sheet 13 0f 19 US 7,233,601 B1 53 51 Up Port T“) Data Data Comrol Not al

Strona 8

Strona 9 - ' message

U.S. Patent Jun. 19, 2007 Sheet 15 0f 19 US 7,233,601 B1 1 5 Mom comma our :3 7| umuu""=1"~ ; Q‘ - l 4 v 3 mt! =~ ‘ . CmtroHN 3 UnitlD

Strona 10 - Modular

U.S. Patent Jun. 19, 2007 Sheet 16 0f 19 US 7,233,601 B1 uum= 4 Control {N “F” AUCntinc Reg 6mm GUT Wm AU€ount=1 T’PStams Reg Cascade Module +1 . Euim

Strona 11 - I I l

Strona 12 - TP‘ieceRev[2l:O]

US 7,233,601 B1 Page 2 US. PATENT DOCUMENTS GB 2268668 A 1/1994 GB 2338155 A 12/1999 6,594,231 B1* 7/2003 Byham et a1. 370/223 GB 2350032 A 11/2000 6,

Strona 13 - Control

U.S. Patent Jun. 19, 2007 Sheet 18 0f 19 US 7,233,601 B1 F ~ An AUCeunt sf 25 $5 being transmmed an the Up pen and a moduie is connected ta me 84:: $3

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Strona 17 - Cascade

Strona 18 - 03$..P uuu?xw

Strona 19

Strona 20 - Coniroi

Strona 21

Strona 22

Strona 23

U.S. Patent 16 n11 16 Jun. 19, 2007 Sheet 1 0f 19 US 7,233,601 B1 14 100 “DEBUG-[1L 1 ‘g 1 ‘Q N Mgmt 11 A 10110011000 /-\/ 12 19 L2 Switch Cascade Ag

Strona 24